*	.text
*	.even

_inter0
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#0,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter1
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#1,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter2
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#2,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter3
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#3,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter4
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#4,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter5
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#5,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter6
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#6,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_inter7
	movem.l	d0-d7/a0-a6,-(a7)
	move.b	#7,_intlev
	jsr	_ciointr
	movem.l	(a7)+,d0-d7/a0-a6
	rte

_initasm
	and.w	#0xf8ff,sr	clear interrupt mask bits in status reg
	rts

	.globl	_inter0
	.globl	_inter1
	.globl	_inter2
	.globl	_inter3
	.globl	_inter4
	.globl	_inter5
	.globl	_inter6
	.globl	_inter7
	.globl	_initasm
	.globl	_ciointr
	.globl	_intlev
	END

/*  */