;;; -*- Mode:LISP; Last-File-Plist:(MODE LISP); Input-List:(#<ART-Q-400 70571503>); Base:10 -*-
numbers in octal
;;		 {	21	PARITY VECTOR (32 bits)
;;		 {	20	PMR (processor mode register 24 bits, read and write;
;;		 {			low 8 bits Configuation Prom, read only)
;;		 {	17	SPY REGISTER (32 bits)
;;		 {	16	MFO ENABLE (reading MFO bus)
;;		 {	15	TREG (output register of TRAM, read only)
;;	RG board {	14	PC (program counter, 16 bits, read only)
;;		 {	13	HPTR (history pointer, 10 bits)
;;		 {	12	HRAM (history ram, 16 bits)
;;		 {	11	TRAM (timing ram)
;;		 {	10	TRAM.ADR (special address register for debug read/write
;;					  of TRAM. 12 bits)
;;		 {	22 CRAM.ADR.MAP (control memory address map, 12 bits)
;;		 {	07 LOW CRAM (low half of control memory, 32 bits)
;;	CM board {	06 HIGH CRAM (high half of control memory, 32 bits)
;;		 {	05 LOW IREG (low half of instruction register, 32 bits,
;;		 {	   	read doesn't use USE.LOW.I)
;;		 {	04 HIGH IREG (high half of instruction register, 32 bits,
;;		 {	  	read doesn't use USE.HIGH.I)
;;		 {	03 MD (memory data register, 32 bits, read only)
;;	MI board {      02 CSM.REG (output register of CSM, 32 bits, read only)
;;		 {	01 CSM.ADR (special address register for debug read/write
;;		 {			of TRAM, low 12 bits, read and write)
;;		 {		& CACHED.PHY.ADR (currently cached physical address,
;;		 {			high 18 bits, read only)
;;		 {		& MEMORY CYCLE STATUS (memory.cycle.pending, bit 31,
;;					and memory.cycle.active, bit 30; read only)
;;		 {	00 CSM (cache state machine, 32 bits)


to get nubus address:

   #xf<rg-slot-in-hex>000000 + (spyloc * 4)

(bb-nd-read-fastest-loop adr)
(bb-nd-write-fastest-loop adr data)

simple bus reads and writes with
  (bus-read adr)
  (bus-write adr data)